1. Field of the Invention
The present invention relates to integrated circuit design, and more specifically to a method and apparatus for amplifying signals in switched capacitor environments.
2. Related Art
Gain stages are often employed to amplify signals. In general, a gain stage amplifies an input signal to generate an amplified output signal. Examples of places where gain stages are employed include, but not limited to, Programmable Gain Amplifiers (PGAs), Analog to Digital Converters (ADCs).
Gain stages are often implemented in switched capacitor environments. A typical switched capacitor environment contains amplifier(s), switches and capacitors driven by clock signals. A capacitor may be used to sample (charged using) an input voltage signal in one phase (xe2x80x9csampling phasexe2x80x9d) of a clock signal.
The sampled signal may be amplified in another phase (xe2x80x9chold or amplify phasexe2x80x9d) of the clock signal by a combination of the capacitors and the amplifier to generate an amplified signal. The amplification factor of the gain stage generally depends on the capacitance values and configuration of the capacitors used with the amplifier. The switches and the clock signals are designed to place the other components of the gain stage in the two phases.
One typical requirement in the implementation of gain stages is the reduction of consumption of electrical power, preferably without degrading of the performance parameters such as bandwidth (i.e., speed with which the signal is amplified), distortion and noise. Therefore, what is needed is a method and apparatus which enable signals to be amplified to a desired degree while minimizing power consumption without potentially degrading the other performance parameters.
An embodiment of an amplification circuit of the present invention is implemented in the context of a Miller Compensated Amplifier which contains two amplifiers, referred to as a pre-amplifier and a main-amplifier. The output of the pre-amplifier drives the input of the main-amplifier. Capacitors are placed across the main-amplifier for stability and are referred to as compensation capacitors. A feedback capacitor may connect the output of the main amplifier to the input of the pre-amplifier.
According to an aspect of the invention, the two amplifiers together operate to amplify an input signal in one phase (xe2x80x9cfirst phasexe2x80x9d) of a clock signal. In another clock phase (xe2x80x9csecond phasexe2x80x9d), the main-amplifier is de-coupled from the pre-amplifier and reused as an independent amplifier to further amplify the signal generated in the first phase.
To achieve such decoupling, two H-switches, which are closed in the first phase and open in the second phase, may be used. The first H-switch may be connected between the output of the pre-amplifier and the input of the main amplifier. The second H-switch may be connected between the output of the main amplifier and the feedback capacitor. By opening the two H-switches, the decoupling may be achieved.
The above amplification circuit may be viewed logically as implementing two gain stages operating in series. That is, the configuration of the circuit in the first phase may be viewed as one gain stage and the configuration of the circuit in the second stage may be viewed as another gain stage. The second gain stage amplifies the amplified output generated by the first stage as described below in further detail.
Another aspect of the present invention enables further amplification in the second gain stage by merely decoupling at least one of the compensation capacitors (xe2x80x9csecond compensation capacitorxe2x80x9d) from the output of the main amplifier. To enable such a feature, a third H-switch may be to used to connect the second compensation capacitor to the output of the main amplifier in the first phase and to de-couple from the output during the second phase. In effect, the amplified signal of the first stage may be sampled onto compensation capacitors in the first phase, and the decoupling enables the signal to be further amplified assuming other compensation capacitors are present for the main amplifier.
In addition, both the capacitors may respectively be coupled to a respective constant voltage during the second phase by a respective S-switch. In general, S-switches are used to provide amplification during the second phase and disconnect in the first stage. Thus, a gain stage may contain an additional S-switch (xe2x80x9cfirst S-switchxe2x80x9d) which enables an input signal to be sampled on the sampling capacitor in the second phase and causes the input signal to be de-coupled from the input signal during the first phase.
In operation, when the first S-switch is closed, an input signal is sampled by the sampling capacitor. When the H-switches are closed and S-switches open in the first phase, the sampled signal is amplified. The amplified signal is sampled on the compensation capacitors as well. The two compensation capacitors operate as compensation capacitors for the main amplifier as well as sampling capacitors for the next phase. When the S-switches are closed and the H-switches open, the second compensation capacitor is disconnected from the output of the main amplifier and further amplifies the amplified signal generated in the first stage.
In one embodiment, the ratio of the feedback capacitance to the sampling capacitor designed to equal 8, and an amplification of 8 may accordingly be attained. The capacitance of the first compensation capacitor may be chosen to equal the capacitance of the second compensation capacitor, with the result that the gain of the second amplification stage equals 2. As the amplified output of the first stage is provided as an input to the second stage, an effective amplification of 16 may be attained.
An amplification circuit operating as described above may consume minimal power since the first amplifier drives low load (only the compensation capacitors) when a high amplification is being attained (8 in the above embodiment) and the main-amplifier drives a high load, while a low gain is attained. As the main amplifier may be used during both the phases, the wastage of electrical power is reduced.
In one embodiment, the input signal is received as a differential signal. An aspect of the present invention enables the common mode voltages of the two amplifier to be set independently. In one embodiment which facilitates such a feature, the pre-amplifier may contain a first p-mosFET and a second p-mosFET, with the source terminals being connected to a supply voltage AVDD. The gate terminals of the first p-mosFET and the second p-mosFET may be biased by a common signal.
The pre-amplifier may further contain a third n-mosFET and a fourth n-mosFET, with the source terminal of the third n-mosFET being connected to the drain terminal of the fourth n-mosFET. The source of the fourth n-mosFET is grounded. The drain terminal of the third n-mosFET may be connected to the drain terminal of the first p-mosFET. This also forms one output terminal of the pre-amplifier. The pre-amplifier may also contain a fifth n-mosFET and a sixth n-mosFET, with the source terminal of the fifth n-mosFET being connected to the drain terminal of the sixth n-mosFET and the source of the sixth n-mosFET is grounded. The drain terminal of the fifth n-mosFET may be connected to the drain terminal of the second p-mosFET. This forms the second output terminal of the pre-amplifier.
The gate terminal of the fourth n-mosFET and sixth n-mosFET may be connected to the first and second output terminal of the pre-amplifier. By sizing the n-mosFET""s appropriately, the common mode voltage (average voltage of the first and second output terminal of the pre-amplifier) can be achieved as desired. Thus the common mode voltage of the pre-amplifier can be made equal to the required input common mode voltage of the main-amplifier. This allows for direct cascading between the pre-amplifier and main-amplifier. Direct cascading generally leads to lower power consumption as additional components do not add to the load, as well as better performance due to reduced complexity.
The above-described amplification circuit may be used in several environments. In one embodiment, the amplification circuit is implemented in an analog to digital circuit (ADC), which in turn is implemented in an analog front end (AFE) of a digital camera. The ADC receives voltage signals representing the charges in a charge coupled device, and converts the charges into digital values. The digital values together represent an image frame.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.